A novel batch fabrication technology for silicon nanowires (NWs) with well controlled cross-section and placement is proposed, based on the use of polysilicon spacers manufactured on lithographically defined patterns. The NWs produced in this way are constituted by polycristalline silicon with controlled doping (with boron or phosphorus) and can have well controlled cross sections ranging from about 30x30 to 100x100 nm2, depending on the process parameters adopted. The entire process, including the Al/Si electrodes used to contact the NWs is CMOS compatible and low-cost, since the nanopatterning is completely realized with the spacer method and is not based on costly techniques such as electron beam or deep ultraviolet lithographies. Moreover, surface micromachining of the silicon nanowires has been obtained in the process, yielding suspended nanowires with variable lengths in the range 3-200 Âµm contacted by Al/Si pads in a four-terminal configuration. In this way, the nano wire thermal conductivity could be measured on-chip yielding, along with electrical resistivity and thermoelectric power, the thermoelectric figure ZT of the nanowires. The best result in this respect was obtained on heavily doped p-type NWs with 90x90 nm2 cross-section, on which a thermal conductivity value around 3 W/mK was obtained, corresponding to a ZT value at room temperature around 0.15, quite in line with some of the best results in the literature obtained with other fabrication techniques.
1 Jan 2012
E-MRS 2012 Spring Meeting-May 14-18