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Article PreviewArticle PreviewArticle Preview300 μm thick 3C-SiC epilayer was grown on off-axis 4H-SiC (0001) substrate with a high growth rate of 1 mm/hour. Dry oxidation, wet oxidation and N 2 O anneal were applied to fabricate lateral MOS capacitors on these 3C-SiC layers. MOS interface obtained by N 2 O anneal has the lowest interface trap density of 3~ 4x10 11 eV-1 cm-2. Although all MOS capacitors still have positive net charges at the MOS interface, the wet oxidised sample has the lowest effective charge density of~ 9.17 x10 11 cm-2.
Trans Tech Publications Ltd
Publication date: 
1 Jan 2019

Fan Li, Valdas Jokubavicius, Michael R Jennings, Rositza Yakimova, Amador Pérez Tomás, Stephen Russell, Yogesh Sharma, Fabrizio Roccaforte, Philip A Mawby, Francesco La Via

Biblio References: 
Volume: 963 Pages: 353-356
Materials Science Forum