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The scaling down of Flash memories can be pursued using the conventional stacked gate architecture only with major changes of the active dielectrics, mainly the inter-poly dielectric (IPD). The required 4-6 nm EOT thickness for the IPD cannot be achieved by the conventional ONO (Oxide-Nitride-Oxide) technology which starts failing in the 10-12 nm range in terms of charge retention properties. Therefore high-k materials are currently investigated for IPD formation in future Flash memories. It is worth noticing that the requirements for IPD are very different from those of the gate dielectrics used in logics. Alumina and alumina based materials (like hafnium aluminates) are among the possible candidates. Promising and tunable electrical and structural properties are achieved for these materials by varying the high-k stack chemical compositions and post-deposition thermal treatments. Different material combinations …
IOP Publishing
Publication date: 
7 Jul 2006

Mauro Alessandri, Rossella Piagge, Stefano Alberici, Enrico Bellandi, Massimo Caniatti, Gabriella Ghidini, Alberto Modelli, Giuseppe Pavia, Enrica Ravizza, Alessandro Sebastiani, Claudia Wiemer, Sabina Spiga, Marco Fanciulli, Vincenzo Fiorentini, Emiliano Cadelano, Giorgia Maria Lopez

Biblio References: 
Volume: 1 Issue: 5 Pages: 91
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