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The threshold voltage (VT) variations induced by the drain bias (Vds) are investigated in polycrystalline silicon thin film transistors (TFTs), with channel length ranging from 20 to 0.4 μm, by combining experimental measurements and two-dimensional (2D) numerical simulations. A careful analysis of the electrical characteristics in both subthreshold and off regime is performed, by taking in account also the effects of the leakage current field enhanced mechanisms on the overall generation-recombination rate. We show that the main causes of VT variations are the drain induced barrier lowering (DIBL) and floating body effects (FBEs), induced by impact ionization. The relative influence of FBEs and DIBL is analyzed by performing numerical simulations with or without including the impact ionization model. A detailed analysis of the 2D Poisson equation has allowed to identify and evaluate the contributions of DIBL and …
American Institute of Physics
Publication date: 
1 Apr 2010
Biblio References: 
Volume: 107 Issue: 7 Pages: 074505
Journal of Applied Physics